In general, a level shift circuit is used in a system LSI provided with a plurality of power supplies. For example, a level shift circuit proposed in Patent Document 1, as shown in FIG. 1, has been known. Besides, the power supply voltage of a system LSI has developed a tendency to decrease in recent years.
On the other hand, in the case of a standardized IO circuit in which it is difficult to reduce the voltage, or an analog circuit in which it is difficult to lower the voltage to ensure an operation margin, the power supply voltage does not decrease. Accordingly, there is need for a level shift circuit capable of performing a stable and high-speed level shift operation even when the potential difference is large.
In order to answer the need, there has been proposed a level shift circuit as for example disclosed in Patent Document 1, which includes a pull-up circuit for supplying a first power supply voltage to a level shift output signal and is controlled based on a level shift input signal.
The inversion of a PMOS cross-coupled latch is difficult when the potential difference between first and second power supplies is large. Accordingly, as shown in FIG. 3, the level shift circuit of Patent Document 1 is provided with NMOS pull-up means, each connected to a first power supply, to facilitate the inversion.
Further, in Patent Document 2, there is disclosed a signal level shift circuit in which PMOS switches, each controlled by a level shift input signal, are arranged between a PMOS cross-coupled pair and a differential NMOS switch.
As described above, the inversion of a PMOS cross-coupled latch is difficult when the potential difference between first and second power supplies is large. Accordingly, as shown in FIG. 2, the signal level shift circuit of Patent Document 2 is provided with the PMOS switches for weakening the bond of the PMOS cross-coupled pair to facilitate the inversion.
[Patent Document 1]
Japanese Patent Laid-Open No. SHO63-152220 (pp. 2 to 3, FIGS. 1 to 3)
[Patent Document 2]
Japanese Patent Application laid open No. HEI6-243680 (pp. 8 to 15, FIGS. 1, 3, 5, 7 and 9)
[Patent Document 3]
Japanese Patent Application laid open No. HEI6-268452 (pp. 4 to 5, FIGS. 1, 3 and 5)